From 5b5720fff384b3c21c3daf7b4cd12b6fb3ba89c3 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Mon, 7 Aug 2017 18:05:59 +0000
Subject: [PATCH] Define VPU services in the Rockchip 3288 DTS files

Automatically enabled by default.

You'll need the external VPU driver to make it work though.

Signed-off-by: Myy <myy@miouyouyou.fr>
---
 arch/arm/boot/dts/rk3288.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 283cce73..e48c34ea 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1173,6 +1173,62 @@
 		};
 	};
 
+	hevc_service: hevc-service@ff9c0000 {
+		compatible = "rockchip,hevc_service";
+		reg = <0xff9c0000 0x400>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		clocks =
+			<&cru ACLK_HEVC>,
+			<&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		clock-names =
+			"aclk_vcodec",
+			"hclk_vcodec",
+			"clk_core",
+			"clk_cabac";
+		/*
+		* The 4K hevc would also work well with 500/125/300/300,
+		* no more err irq and reset request.
+		*/
+		assigned-clocks = 
+			<&cru ACLK_HEVC>,
+			<&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		assigned-clock-rates =
+			<400000000>,
+			<100000000>,
+			<300000000>,
+			<300000000>;
+
+		resets = <&cru SRST_HEVC>;
+		reset-names = "video";
+		power-domains = <&power RK3288_PD_HEVC>;
+		rockchip,grf = <&grf>;
+		dev_mode = <1>;
+		iommus = <&hevc_mmu>;
+		iommu_enabled = <1>;
+		status = "okay";
+		/* 0 means ion, 1 means drm */
+		allocator = <1>;
+	};
+
+	hevc_mmu: iommu@ff9c0440 {
+		compatible = "rockchip,iommu";
+		reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hevc_mmu";
+		clocks = <&cru ACLK_HEVC>,
+			<&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		clock-names = "aclk", "hclk", "clk_core", "clk_cabac";
+		power-domains = <&power RK3288_PD_HEVC>;
+		#iommu-cells = <0>;
+	};
+
 	qos_gpu_r: qos@ffaa0000 {
 		compatible = "syscon";
 		reg = <0xffaa0000 0x20>;
@@ -1243,6 +1299,38 @@
 		reg = <0xffaf0080 0x20>;
 	};
 
+	vpu_service: vpu-service@ff9a0000 {
+		compatible = "rockchip,vpu_service";
+		reg = <0xff9a0000 0x800>;
+		interrupts = 
+			<GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_enc", "irq_dec";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		power-domains = <&power RK3288_PD_VIDEO>;
+		rockchip,grf = <&grf>;
+		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+		reset-names = "video_a", "video_h";
+		iommus = <&vpu_mmu>;
+		iommu_enabled = <1>;
+		dev_mode = <0>;
+		status = "okay";
+		/* 0 means ion, 1 means drm */
+		allocator = <1>;
+	};
+
+	vpu_mmu: iommu@ff9a0800 {
+		compatible = "rockchip,iommu";
+		reg = <0xff9a0800 0x100>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vpu_mmu";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk", "hclk";
+		power-domains = <&power RK3288_PD_VIDEO>;
+		#iommu-cells = <0>;
+	};
+
 	gic: interrupt-controller@ffc01000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
-- 
2.13.0

